As the trend toward higher integration levels in semiconductor device fabrication continues, the use of trench structures in semiconductor substrates has increased. Trench structures are used for a variety of different device components, including vertically oriented transistors, isolation structures, such as shallow trench isolation (STI) structures, deep trench isolation (DTI) structures, capacitors, and the like. Accordingly, the etching of trench structures in a semiconductor substrate is an important part of the overall process of manufacturing many integrated circuit devices.
The fabrication of trench structures, and in particular deep trench structures, presents a number of process requirements requiring adequate process control. During trench formation, it is important to control the sidewall profile as the trench is formed in the substrate. For example, undercutting of the masking pattern used to define the trench opening can result in an undesirable widening of the trench near the substrate surface. Also, in the fabrication of deep trench structures, a reasonably high etch rate needs to be maintained in order to provide acceptable process throughput. Resist loading can become a problem when etching deep trench structures due to erosion of the resist during the etching process.
Related to maintaining a high etch rate is the ability to achieve a desired trench depth in the substrate. Many semiconductor integrated circuits require trenches have depths of, for example, 80 to 100 microns. In addition to being very deep, these trenches also have very small diameters leading to large aspect ratios. The formation of high aspect ratio trench structures requires that the masking layer used to define the trenches withstand the etch process conditions necessary to rapidly etch the trenches deep into the substrate. Mask erosion during etching can lead to undesirable narrowing of the trench and, in extreme cases, blocking of the bottom of the trench, which results in a trench that is not etched to the desired depth.
In the fabrication of dynamic-random-access-memory (DRAM) devices, deep trenches are typically formed for capacitor fabrication. The geometry of the capacitor trench is an important factor in the capacitance value of the capacitor in a DRAM memory cell. In particular, it is desired that the capacitor in each DRAM memory cell have a similar capacitance value, so that the DRAM memory array stores electrical charge uniformly across the array.
Given the increasing importance of trench fabrication for a variety of semiconductor applications, improved fabrication technology is necessary that will enable the reliable formation of deep trench structures having substantially uniform geometrical characteristics.